Multi-level step and flash imprint lithography for direct patterning of dielectrics

Modern integrated circuit fabrication uses the dual damascene process to create the copper interconnects in the Back End of the Line (BEOL) processing. The number of wiring levels is increasing to eight or more in advanced microprocessors, and the complexity and cost of the BEOL processes is growing rapidly. An approach to dual damascene processing using Step and Flash Imprint Lithography (S-FIL (R)) in conjunction with Sacrificial Imprint Materials (SIM) offers the ability to pattern two levels of interconnect structures simultaneously. By, using a multi-level imprint template built with both the via and trench structures, one imprint lithography step can produce the same structures as two photolithography steps, greatly reducing the number of patterning process steps in the BEOL layers. This paper presents progress in formulation of new sacrificial imprint materials and the development of S-FIL and etch processes to incorporate the SIM strategy. The SIM is formulated as a two-component system, with a tunable etch rate adjusted by the ratio of the monomer and cross-linker components. High quality imprints were produced with a multi-level template on wafers with blank films of black diamond (R) dielectric material. The quality of the multi-level pattern transfer from the SIM into black diamond was evaluated.