Advantages of Faceted P-Raised Source/Drain in Fully Depleted Silicon on Insulator Technology

Fully Depleted Silicon-On-Insulator (FDSOI) technology is a strong competitor in particular for RF applications, providing high performance at low manufacturing cost. In this technology, PFET devices utilize an epitaxially grown pFET raised source/drain (pRSD). However, the pRSD structure adds to the parasitic capacitance to the gate which is a detractor of RF performance. We demonstrate a faceted epitaxial RSD process that reduces this parasitic capacitance (C-Miller) by up to -25% and further improves the already high RF pFET f(max) by +18%. In addition, we show improved defectivity (-80% non-selective growth defect count reduction), and reduced within-wafer C-Miller variability (1-sigma reduced by -42%). All of these make faceted pRSD a powerful technique to significantly improve device performance in FDSOI.