Model Implementation for Accurate Variation Estimation of Analog Parameters in Advanced SOI Technologies

Analog design uses transistors with longer channel length for high performance. Transconductance (g(m)), Output Resistance (R-out) and Intrinsic Gain (g(m) x R-out) form the metric to gauge this performance. It is critical to design these circuits for manufacturing variability. This work presents a systematic compact modeling approach to capture analog variation in compact models. We show that the variation in R-out is very well correlated to the variation in DIBL, especially if the transistors are biased at around 100-200mV gate-overdrive. We observe that this correlation becomes stronger as the channel length increases. We propose a sub-circuit based approach to model DIBL variation in the corner models. This method provides accurate variability estimates of g(m) and R-out in the compact models for 65nm and 45nm technologies.