The Velopix Asic
JOURNAL OF INSTRUMENTATION(2017)
Abstract
VeloPix, a 130 nm CMOS technology chip with data driven and zero suppressed readout, will be used as a readout chip for the hybrid pixel system of the LHCb Vertex Locator (VELO) upgrade. The upgrade, scheduled for LHC Run-3, will enable the experiment to be read out at 40 MHz in trigger-less mode, with event selection being performed in the CPU farm. The highest occupancy ASICs will experience rates of more than 900 Mhits/s, and the closest pixels are 5.1 mm from the LHC beams. This paper will present the VeloPix ASIC along with the first test results without a sensor.
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Key words
Digital electronic circuits,Front-end electronics for detector readout,VLSI circuits
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