TCAD in CTF parameter study of SOI tunnelling FET using full factorial design

The first approach which employed full factorial design for DOI Tunnel FETs critical to function (CTF) parameters study is presented in this paper. This work focused on the state performance improvement for SOI tunnel FETs. TCAD Sentaurus was used to conduct Design of Experiment (DOE) by deploying silicon thickness, EOT thickness and gate oxide material as factors to investigate the responses. Selective DOE work only on silicon and investigation was carried out on Ion, Ioff and trans-conductance as responses. Data extracted from the simulation results revealed that EOT thickness (B) and gate oxide material (C) were the most influential process variables to on current, off current and trans- conductance.