CMP $ im: A Pin based on the fly multi core cache simulator

Chip multiprocessors are the next attractive point in the design space of future high performance processors. There is a growing need for simulation methodologies to determine the memory system requirements of emerging workloads in a reasonable amount of time. To explore the design space of a CMP memory hierarchy, this paper presents the use of binary instrumentation as an alternative to execution-driven and trace-driven simulation methodologies. Using the binary instrumentation tool, Pin, we present CMP $ im to characterize cache performance of single-threaded, multi-threaded, and multi-programmed workloads at the speeds of 4-10 MIPS. For memory intensive single-threaded workloads, the cache performance reported by CMP $ im is three orders of magnitude faster and within 4% of an cycle-accurate x86 performance model.