Ccsds 131.2-B-1 Telemetry Transmitter: A Vhdl Ip Core And A Validation Architecture On Board Rtg4 Fpga

During the last years, improvement in the resolution of Earth observation satellite instruments has been leading to the necessity of high throughput transmitters, featuring efficient encoding and modulation schemes. For that reason, the Consultative Committee for Space Data Systems (CCSDS) issued the CCSDS 131.2-B-1 standard describing the architecture of a flexible telemetry transmitter featuring Serially Concatenated Convolutional Codes (SCCCs). Such flexibility allows CCSDS 131.1-B-1 implementations to take full advantage of the channel by dynamically changing the coding-rate and type of modulation (Adaptive Code and Modulation, ACM).This work presents a VHDL Telemetry Transmitter IP Core fully compliant to the CCSDS 131.2-B-1 standard. The IP Core is technology independent and as such can be fitted on different Field Programmable Gate Arrays (FPGAs), including space grade devices, realizing a broad spectrum of solutions that differ in terms of transmission throughput, radiation hardness and cost figures. In particular, this work shows that the IP Core is able to reach 259.3 Mbaud and 1355 Mbit/s data transfer on the Microsemi RTG4 FPGA. To verify the IP Core functionalities on board the different FPGAs, register-transfer level (RTL) and post-layout simulations were performed through a custom verification environment. The latter allowed 100% functional and code coverage according to a dedicated test plan. Finally, the IP was validated through an appropriate validation system on board the Microsemi RTG4 FPGA exploiting a hardware/software co-design approach.