0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop

This brief presents a quadrature resonant clock generator for driving four 4.3-mm load wires with tuning capacitors and an amplitude control feedback loop. By using frequency tuning capacitors, which reduce the mismatch in operation and LC resonant frequencies, the proposed clock generator offers power reduction by 20-25% compared with conventional CMOS clock driver and by 23-34% compared with conventional CML clock driver over a wide voltage swing. The amplitude control feedback loop, which determines the bias current of the negative gm cell, maintains the constant optimized clock swing over wide PVT variations. Measurement result from the prototype chip fabricated in 65 nm CMOS shows that total power consumption of the proposed quadrature resonant clock is 11.92 mW in 7-GHz operation with four 559-fF load wire capacitances. Measured period jitter is 573.6 fsrms and phase noise at 1MHz offset is -138.37 dBc/Hz.