Influence of Solder Layer Void on Thermal Stability for Power Semiconductor Device

Solder layer void is one of the causes of thermal failure for power semiconductor device. In this study, influence of solder layer void with different diameter and position on the thermal stability for power device in different package form is observed and simulated by HTRB (High Temperature Reverse Bias) test, X-ray scanning, and ANSYS Workbench. The conclusion provides that: 1. Larger diameter void is more likely to cause burn out around themselves; 2. When the diameter of void is larger than 0.3mm, chip maximum temperature of TO-220F rises by more than 2.75%, TO-220 is up over 1.41%. Void affect the thermal reliability of power semiconductor device obviously, with the increase of void diameter; 3. The void at the center position is more likely to cause device burn out. Consequently, solder layer void diameter should be controlled. Meanwhile, it is necessary to eliminate void in the center of the chip to avoid reliability risk in power device package.