FPGA IMPLEMENTATION OF HYBRID SYSTEM USING TIMING ATTACK RESISTANT CRYPTOGRAPHIC TECHNIQUE

In this article, a hybrid system is presented for security and reliability of data while it transmits over communication channel. In this proposed system Brackets, Order, Division, Multiplication, Addition and Subtraction (BODMAS) sequence of operations are used as an encryption algorithm. The data reliability is obtained by using orthogonal codes. This coding technique improves the percentage of error detection and correction rates up to 99.9999%. The segmented decoder technique is used to reduce clock cycles. The clock cycles required to decode the received data is equal to half of the orthogonal code length. The results show that our proposed system resistant to timing attacks for variable data inputs.