Impact of barrier film characteristics on Vramp breakdown voltage and TDDB lifetime of 65 nm node Cu/Low k interconnects

The effect of various PVD processes on TDDB and Vramp test performances was studied for 65nm node structures to identify the main barrier film quality drivers for good breakdown voltages and lifetimes. Different barrier film schemes, namely, barrier first, pre-clean first, insitu and ex-situ etch-back, barrier deposition only, and multiple depositions and etch steps are compared in terms of TDDB and Vramp performance. It is demonstrated that with the optimization of the PVD process, significant improvement in TDDB and Vramp can be achieved. Investigation into the commonality among best performing TDDB and Vramp splits with respect to above schemes revealed that all processes with low "on-wafer" RF bias-voltage during the etch-back step or deposition-only step displayed the best Vramp/TDDB performance. When the "on-wafer" bias is relatively high, the density of the bartier film is lower and hence resistance to Cu ion diffusion into the dielectric is poorer. The reliability study clearly finds a strong correlation between the PVD process and TDDB at 65 nm technology node, which is not commonly seen at 90 nm and above nodes.