Electrical and reliability evaluation of Cu/low-k integration: Exploration of PVD barrier/seed and CVD SiC(N,H) cap depositions

This paper describes a 90nm node Cu/CVD low-k interconnect technology integrated with PVD diffusion barriers, PVD Cu seed and CVD SiC(N,H) post-CMP cap dielectric. The effects of various PVD barrier/seed and the CVD cap processes on electrical and reliability performance are reported. Significant decreases of both metal line- and via contact-electrical resistances were observed by thinning down the barrier thickness without a decrease in reliability performance. Impacts of sputter etch integration scheme on electrical yield and reliability were also studied. The duration of thermal soak prior to the dielectric cap deposition and the cap deposition process conditions were also checked in the study. Based on all the above data, we demonstrated a wide and robust process window improvement on current 90nm CMOS technology with Cu/CVD low-k BEOL.