Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision
2020 57th ACM/IEEE Design Automation Conference (DAC)(2020)
摘要
This paper presents 6T SRAM cell-based bit-parallel in-memory computing (IMC) architecture to support various computations with reconfigurable bit-precision. In the proposed technique, bit line computation is performed with a short WL followed by BL boosting circuits, which can reduce BL computing delays. By performing carry-propagation between each near-memory circuit, bit-parallel complex computations are also enabled by iterating operations with low latency. In addition, reconfigurable bit-precision is also supported based on carry-propagation size. Our 128KB in/near memory computing architecture has been implemented using a 28nm CMOS process, and it can achieve 2.25GHz clock frequency at 0.9V with 5.2% of area overhead. The proposed architecture also achieves 0.68, 8.09 TOPS/W for the parallel addition and multiplication, respectively. In addition, the proposed work also supports a wide range of supply voltage, from 0.6V to 1.1V.
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关键词
In-Memory Computing,Processing-In-memory,Read Disturb,Bitline Computing,Short Pulse WL
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