Deterministic Shuffling Networks to Implement Stochastic Circuits in Parallel

Stochastic computing (SC) in recent years has been defined as a digital computation approach that operates on streams of random bits that represent probability values. SC can perform complex tasks with much smaller hardware footprints compared with conventional binary methods, but previous methods on SC circuits operated on serial bit streams, which leads to high-latency implementations. This article presents a significant improvement over previous work; it provides a deterministic parallel bit shuffling network that can use a simple deterministic thermometer encoding of data, resulting in zero random fluctuation and high accuracy, yet keeping the output bit-stream length constant. We use core “stochastic” logic circuits that do not employ constant coefficients, making them significantly smaller than traditional stochastic logic that use a significant amount of resources to generate such coefficients. Our experiments show that compared with previous SC methods, our method has up to 3x smaller mean absolute error, and better area x delay and power efficiency. Compared with conventional binary methods, our method is better in terms of area x delay at 8-bit resolution. It shows better power efficiency (40x, 18x, and 8x Gops/W at 8-, 10-, and 12-bit resolutions) compared with conventional binary.