A Scalable Multi-TeraOPS Core for AI Training and Inference

IEEE Solid-State Circuits Letters(2018)

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摘要
This letter presents a multi-TOPS AI accelerator core for deep learning training and inference. With a programmable architecture and custom ISA, this engine achieves >90% sustained utilization across the range of neural network topologies by employing a dataflow architecture to provide high throughput and an on-chip scratchpad hierarchy to meet the bandwidth demands of the compute units. A custom ...
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关键词
Training,Deep learning,Computer architecture,Solid state circuits,Bandwidth,Hardware
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