DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options

Jeffrey D. Black,Dolores A. Black, Nicholas A. Domme,Paul E. Dodd,Patrick J. Griffin,R. Nathan Nowlin,James M. Trippe,Joseph G. Salas,Robert A. Reed,Robert A. Weller,Andrew M. Tonigan,Ronald D Schrimpf

IEEE Transactions on Nuclear Science（2020）

引用 3|浏览50

暂无评分

摘要

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical ...

查看译文

关键词

Layout,Logic gates,Implants,MOSFET,Ions,Silicon

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要