Recent Advances in Industry and Experimental Research in Processor Level Error Detection and Recovery

Transient faults have traditionally been associated with the corruption of stored data values. This phenomenon has been reported as early as 1954 in adverse operating conditions such as near nuclear bomb test sites and later in space applications [3],[1]. Since 1978, dense memory circuits, both DRAM and SRAM, have been known to be susceptible to soft errors caused by alpha particles from IC packaging [5] and cosmic rays [2]. A hardware device can usually recover its full capability following a transient failure, but such failures are no less catastrophic for the correct execution of a program because a corrupted intermediate value, if not handled, can corrupt subsequent computations. Over the years, measures to protect against soft errors in memory devices have evolved to include physical techniques in cell/gate design [4] and packaging materials [6], as well as error correction codes (ECC). Today, these techniques are commonplace even in commodity PC memories. Soft-error rates vary greatly depending on device types and operating conditions, but current estimates are typically on the order of one failure per one million hours.