Estimating Operational Age of an Integrated Circuit

Recycling of used ICs as new replacement parts in maintaining older electronic systems is a serious reliability concern. This paper presents a novel approach to estimate the operational age of CMOS chips by measuring I D D Q , the quiescent current from power supply or the total leakage current in steady state. This current decreases as the circuit ages, largely due to the increase in the magnitude of the PMOS transistor threshold voltage caused by negative bias temperature instability (NBTI). We exploit the fact that the impact of NBTI on an individual transistor depends upon the operational stress based upon the duration of its ON state. Novelty of our technique is a normalized difference, Δ I , computed from current measurements at two input test patterns and is proposed as a self referencing circuit age indicator. The first pattern is chosen such that its I D D Q is controlled by a large number of minimally stressed PMOS transistors; for the other the I D D Q is controlled by approximately equal number of highly stressed PMOS transistors. The difference between these two I D D Q values increases with the circuit age. This approach requires no hardware modification in the circuit and, hence, can be applied to legacy ICs. Simulation results show that we can reliably identify recycled ICs that have been used for as little as six months.