Bounded Verification of Simulink Models

Simulink is the de-facto standard for model-based software development in many domains. With the ever-increasing size and complexity of the models, it is very beneficial to apply highly automated and rigorous verification techniques based on formal methods, which go beyond simulation, in order to check whether a model satisfies its specification. While tools employing such methods do exist for Simulink, one can mainly check errors such as integer overflow, array access violations, etc., or statistical properties. In this paper, we show how Simulink models can be formally analyzed against invariance properties using bounded model checking reduced to satisfiability modulo theories solving. In its basic form, the technique provides means for verification of an underlying model over bounded traces rigorously, however, in general the procedure is incomplete. We identify common Simulink block types and compositions by analyzing selected industrial models, and we show that for some of them the set of non-repeating states (reachability diameter) can be visited with a finite set of paths of finite length, yielding the verification complete. We complement our approach with a tool, called SyMC that automates the following: i) calculation of the reachability diameter size for some of the designs, ii) generation of finite (bounded) paths of the underlying Simulink model and their encoding into SMT-LIB format and iii) checking invariance properties using the Z3 SMT solver. To show the applicability of our approach, we apply it on a prototype implementation of an industrial Simulink model, namely Brake by Wire from Volvo Group Trucks Technology, Sweden.