Design and Analysis of Low Power Fixed-Width Multiplier Using Reduced Precision Redundancy Block (RPR)

This paper suggests a low power fixed-width multiplier using a reduced precision redundancy unit (RPR) for VLSI signal processing applications. RPR consists of a reduced precision module and a full precision module. The result of the reduced precision is considered as the correct output when the source output computes falsely. The proposed RPR fixed-width multiplier can satisfy the demand for accuracy, area efficiency, processing speed, and low power consumption. The precision of the proposed multiplier will be enhanced by the RPR logic. The compensation bias consists of probability and statistics. To avoid the truncation error many types of rounding methods are employed. The proposed RPR fixed-width multiplier is installed in the FIR filter design for various signal processing applications. The detailed analysis of the suggested multiplier gives 30% power reduction and 46.54% area reduction as compared with the different techniques.