Dual chip in single module solid-state power amplifier design for compact transmitter architecture

At present, the high power solid-state technique transmitter design are composed of hundreds parallel combined single chip for hundreds Watts power modules to achieve enough output power. Although the large numbers can bring high redundancy during system operation, the power hungry of next generation RF system of accelerator would need much more modules to satisfy its power requirement. Huge amount of power modules would bring the complexity and difficulty in power combining, system construction, management and maintenance. To overcome this disadvantage, upgrading the power level of a single module could be the solution. Besides depending on the power level growing with technology advancement in semiconductor industry, a circuit level solution to combine dual chip in advance in a single PCB board is proposed to produce twice power of single chip. Four power dividing/combining methods are designed and measured in this article. INTRODUCTION In accelerator field, the solid-state RF power sources are becoming popular for accelerating sub-systems, such as storage ring of LNLS and SOLEIL [1], booster of SOLEIL [2], LINAC of ELBE [3] and even beam chopper of J-PARC [4]. The basic working principle of the above solid-state amplifier circuits are adopting coaxial balun in CW [1-2] and printed Marchand balun in pulse [4] for push-pull operation. The adopted solid-state technology can extend from VHF to L-band in accelerator application. The power level available from basic solid-state power amplifier (SSPA) unit is mainly determined by single chip module for continuous wave (CW) operation. However, two or more chips in single module can be found for pulse operation [4]. The possible reason for this is that the size of multi-SSPA units for CW operation is not small enough to be integrated together within one module. The other could be the cooling structure during development procedure is not intended for multi-amplifiers within one module. Since the compact round planar balun at 500MHz has been proposed by NSRRC in 2012 [5]. The integration of dual power transistor chips within one module without expanding too much area becomes applicable (less than 3U/133.3mm in width). In Fig. 1, without sacrificing the accessory bias components, the estimated size reduction using planar balun (139*108mm^2) can reach 50% when comparing to that using coaxial type balun (175*180mm^2). Thus, with the compact planar balun, dual or more chips integrating within one SSPA module become attractive. This article will discuss four planar two-way power splitting/combining methods for their characteristics as a basic study for dual chip combination within one SSPA module for double output power. With double output power, the total number of solid-state transmitter could be reduced in half for the same power level or twice the output power with the same module numbers.