Modeling Stress-Induced Variability Optimizes IC Timing Performance

Many design teams migrate to advanced IC process nodes to increase performance while reducing area and power. Timing performance and predictability can be compromised, however, if there’s too much systematic variability. Fortunately, systematic variability can be modeled and mitigated if one understands the causes. A leading cause of systematic variability at 45 nm and below is the application of mechanical stress to transistors.