An improved parallel archutecture for mpeg-4 motion estimation in 3 6 mobile applications

A'high-parallel VLSl core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-registerhuffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QClF video sequences in real time at 1 MH2 clock rate and using 15.5 Mbyteds memory bandwidth.