100 Gb / s CFP coherent transceiver enabled by power-optimized DSP

Summary We demonstrate a fully engineered 100 Gb/s CFP coherent transceiver enabled by power-optimized digital signal processing. We confirmed stable real-time SMF transmission up to 840 km with 1/3 power dissipation compared with a 5×7 MSA transceiver. Introduction Challenges of lower power consumption of digital coherent technology attract more attention in order to expand its application to metro access networks and WDM links between data centers. In these applications, it is desirable to implement a digital coherent transceiver in pluggable form factor that has been standardized for client interface [1] [2]. In order to realize the pluggable digital coherent transceiver, as well as miniaturization of the optical devices, drastic power reduction of the DSP ASIC is required [3]. In this paper, we demonstrate the performance of a newly prototyped low-power DSP ASIC, an InP DPIQ modulator module, and a compact integrated coherent receiver (ICR) module which have been successfully packaged in a pluggable form factor module. By using these CFP-transceiver devices, real-time and stable 100 Gb/s DP-QPSK transmission over 70 to 840 km SMF has been confirmed. Low-power DSP ASIC Fig. 1 shows the block diagram of the low-power DSPASIC. In addition to the conventional ADC/DSP cores [4], this device includes DACs to output the 28/32G × 4ch analog waveforms, a framer to accommodate 100GE signal into OTU4 frame, and a spectral shaping filter that realizes spectrally efficient Nyquist pulse. The 31 × 31 mm 2 BGA-package occupies less than 30% footprint as compared to a combination of a DSP (37.5 × 37.5 mm 2 ) and an OTN-framer (42.5 × 42.5 mm 2 ) ASICs available today. The latest CMOS process technology has made single-chip implementation of 150-million-gates feasible. Functional optimization with regard to power consumption has been realized with selectable FEC and CD compensation options to cope with their trade-offs on performance that requires computational complexity. Fig. 2 shows possible combinations of functions in the newly-prototyped DSP ASIC. Client signal types and the use of Nyquist filtering are also selectable, and by choosing the optimum functional combination for power and performance, the single DSP ASIC can be used in different types of applications, spanning from short-range of 100 km or less to longdistance of more than 2,000 km. InP DP-IQ Modulator In order to shrink the footprint, we employed an InPbased modulator in the transceiver. Fig. 3 shows the configuration of our InP modulator module. The two nested Mach-Zehnder modulators (MZMs) for the orthogonal polarizations are integrated in one chip. The chip is equipped with four pairs of differential RF electrodes, four pairs of phase shifters for child MZMs and two pairs of phase shifter for parent MZMs.An offchip polarization multiplexer is used to combine the two outputs from the chip. The fabricated modulator module is shown in Fig. 4(a). The size of the module body is 12 mm × 39 mm × 6.5 mm excluding the nodes and tabs. The module has surface mounted type (SMT) interfaces for RF drive and Fig. 1. Block diagram of the low-power DSP SD-FEC (LDPC) 7% HD-FEC CD compensation (ps/nm)