Supervia: Relieving Routing Congestion using Double-height Vias

With increase in transistor packing density and use of uni-directional metal routing, resources on local metal layers are increasingly limited. A major contributor to routing congestion is the minimum metal area (minArea) design rule, which has been steadily increasing over the past few technology nodes. For a net which crosses multiple metal layers (e.g., M2 to M4), polygons on intermediate layers (e.g., M3) i.e. via landing pads must satisfy the minArea rule; this creates unnecessary routing blockage, which can lead to area overhead. In this work, we investigated the benefits of introduction into the BEOL stack of a new “supervia” structure, namely, a double-height via spanning two metal layers without a landing pad on an intermediate metal layer. We study the benefit of supervia using (i) routing clip-based evaluation using an optimal ILP-based router (OptRouterSV) and (ii) chip-level evaluation using a commercial routing tool in conjunction with MILP-based supervia aware legalization. With the latter, if the legalization approach fails, the failures are localized to clips, which are then routed optimally using OptRouterSV. Our results suggest that when the P&R tool is allowed to generate via structures which optimizes for minArea in stacked vias, using supervia can save ≥2% of the chip area whereas in absence of this option, supervia can save as much as 20% of the chip area.