Wire Load Model for Rapid Power Consumption Evaluation in Early Design Stage of Via-Switch FPGA

This paper proposes a wire load model for via-switch FPGA to allow simulation-based power estimation before routing. Via-switch FPGA is expected to achieve a dramatic improvement in the area, delay, and power compared with conventional SRAM-based FPGA. To estimate the power consumption of an application circuit mapped on a via-switch FPGA, time-consuming routing process was needed before circuit simulation. Using the proposed postplacement simulation flow, runtime for power estimation is reduced by 63.8% on average compared with the conventional post-routing simulation flow, with 11.8% degradation of estimation error on average.