Lithography challenges for leading edge 3d packaging applications

Leading edge consumer electronic products drive demand for enhanced performance and small form factors. This in turn drives manufacturing requirements for all aspects of semiconductor device fabrication. As the cost of front end device manufacturing continues to escalate rapidly with each new technology node, semiconductor manufacturing companies are now also focusing on packaging technology to deliver improved performance and reduced form factor. A number of innovative technologies are being developed to support increasing packaging density requirements. It is anticipated that advanced three dimensional (3D) packaging technologies such as TSV (Through Silicon Via) manufacturing will play a critical role in future semiconductor device miniaturization. Advanced system in package (SiP) capability is now viewed as a key strategic technology by device manufacturers and foundry companies. Several SiP techniques will require TSV to provide high density vertical interchip wiring of multiple device stacks. These vias need to be freely placed in the device which creates a requirement for tight registration of the back-to-front side device alignment. This paper investigates the lithography challenges associated with TSV fabrication for various devices structures. Silicon test wafers have been fabricated with a variety of films to evaluate the back-to-front side wafer alignment. The reference layer is defined in a standard damascene copper process and protected with a passivation layer. Next the wafers are flipped, bonded, and thinned to various thicknesses. Some wafers are also processed through a chemical mechanical polish (CMP) step. The importance of surface quality is analyzed since CMP is required to create an optically smooth surface and this processing step is expensive which impacts overall fabrication cost. Images of the embedded alignment target are shown for various silicon thicknesses and wafer surface quality. Experimental backto-front alignment metrology data is shown as a function of silicon thickness for various film stacks.