Conduction and Breakdown Mechanisms in Low-k Spacer and Nitride Spacer Dielectric Stacks in Middle of Line Interconnects

To achieve robust middle of line interconnects in advanced CMOS technology, electrical reliability of the dielectric stacks consisting of low-k spacer and nitride spacer dielectrics between gate metal and local interconnect metal is critical. To mimic this dielectric system, this work focuses on the stacks having SiN on top of SiO 2 with the total thickness below 15nm. The electrical conduction is proven to be determined by the electron injection interface. Additional defects are found in the SiN layer close to the SiO2 interface as the result of SiN deposition on SiO2. These defects assist electron transport when the electrons are injected from the SiN side. In the time dependent dielectric breakdown assessment, the Weibull slope, β, behaves differently under positively and negatively biased stresses where +β depends on both SiO 2 and SiN thicknesses, but -β is mainly dependent on the SiO 2 thickness and is only weakly dependent on the SiN thickness. The field acceleration factor, +m and -m, show similar relations versus the equivalent SiN thickness. Due to the much higher electric field distributed in the low-k layer in dielectric stacks, the performance of low-k spacer layer is proven to be crucial for the stack reliability.