Rotary Register File: A Micro-Architectural Primitive on FPGA

Modern FPGAs provide playgrounds for overlay architectures optimized for different application domains. Competitive overlays rely on micro-architectural primitives not only offering logic abstractions, but also those best leveraging the inherent physical architectures of FPGAs. In this paper, we propose a new primitive, named rotary register file (RRF), optimized for circular memory accesses often found in signal processing, machine learning, and error-correcting code applications. We demonstrate that the proposed primitive could offer a simple form of folded parallelism, which enables a spectrum of design space instances between the most serial and parallel designs, while simultaneously avoiding the curse of multiplexers in FPGAs.