A Low Power 7T SRAM cell using Supply Feedback Technique at 28nm CMOS Technology

The downscaling of CMOS technology creates critical issues like power dissipation and stability in static random access memory (SRAM). Which eventually degrades the performance of the SRAM cell. Hence to address the issue of data stability and power dissipation, this paper proposed a new seven transistors (7T) SRAM cell to increases the write ability and reduces the static power consumption or dissipation using supply feedback transistor. Furthermore, the read stability also increased using isolated read port. The stability of the proposed design under hold mode of operation has been slightly decreased because of a reduction in the power supply. This has been observed that the RSNM, WSNM, and write delay of proposed 7T is enhanced by 1.8x, 1.10x, and 1.16x respectively as compared to conventional 6T SRAM cell at 0.9 cell supply voltage. Whereas the HSNM, read delay, and static power consumption or dissipation of proposed 7T is decreased by 1.08x, 1.3x, and 1.5x respectively in comparison to basic 6T SRAM cell at the same power supply. The newly designed 7T SRAM cell has been calibrated in the cadence virtuoso environment using a 28nm CMOS technology nod