Study On The Single-Event Upset Sensitivity Of 65-Nm Cmos Sequential Logic Circuit

This study uses a pulsed laser to investigate the sensitivity of a sequential logic circuit to a Single-Event-Upset (SEU) under different supply voltages, clock frequencies, and circuit architectures. The experimented sequential logic circuit is a D flip-flop chain manufactured in 65-nm bulk CMOS technology. The results indicate that as the voltage decreases, the SEU sensibility of the circuit increases, and in particular at low voltage ranges, it increases significantly. Additionally, the effect of clock frequency on the sensitivity of the sequential logic circuit is mainly related to the propagation of Single-Event-Transients (SETs) that are generated in combinational logic circuits. It was also found that, the Set-architecture circuit is more sensitive to SEUs during the data "0" test, while the Reset-architecture circuit is more sensitive to SEUs during the data "1" test. In addition, the failure mechanisms of SEU induced by Set-structure and Reset-structure are revealed using SPICE simulations.