A high-resolution Vernier delay generator using delay-adjustable carry chains on FPGAs

Delay generator (DG) generating a digitally programmed time interval acts as the core component in various modern physical experiments. Most traditional designs are based on application specific integrated circuit (ASIC) platform causing long development period and high cost. This work presents a high-resolution Vernier DG architecture based on field programmable gate array (FPGA) platform, which utilizes a novel delay line structure built on multiplexed carry chain. The carry chain structure guarantees the resolution rather small. The multiplexer laid next to the carry chain makes the actual delay of the delay line dynamically adjustable. This structure can be automatically compiled by PC without manual intervene while maintaining very high resolution. A DG prototype circuit was implemented on a Stratix III FPGA and experimental tests were conducted to evaluate the performance. The obtained resolution is 23.9 ps, the differential nonlinearity (DNL) lies in the range of -0.62 least significant bit (LSB) ~ 0.59 LSB and the integral nonlinearity (INL) lies in the range of -0.14 LSB ~ 0.01 LSB. All the performances show state-of-the-art quality.