A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration.

This brief presents a 7-b 32-GS/s successive approximation register analog-to-digital converter (ADC) using a massive time-interleaving (TI) architecture. For low-skew multi-phase clocks, generation utilizing a delay-locked loop (DLL) phase-detector (PD) with a reduced offset is proposed to minimize skew between the clocks. Different clock path delays caused by distributed sub-ADCs over a large ar...