A 0.5V-to-0.9v 0.2Ghz-to-5ghz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology.
2020 IEEE Custom Integrated Circuits Conference (CICC)（2020）
关键词
Ultra-low power,digitally-assisted,phase-locked loop,PLL,SoC,IoT,fast locking,wide output clock frequency range,wide reference clockfrequency range
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