Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs
2020 2ND IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS 2020)（2020）
Key words
energy-efficient accelerator design,deep learning applications,energy constrained edge devices,deep networks,resource utilization,flexible hierarchical on-chip interconnection architecture,PE-tiles,energy consumption,off-chip DRAM,distributed 3D-SRAM,configurable ring-based unicast global network,PE tile,compact sparse CNN,MobileNetV2
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