Characterization of a newly developed readout electronics system for strip detectors

The aim of the present paper was to investigate the performance of a newly developed general purpose strip detector system, and its energy resolution improvement provided by custom characterization and calibration procedures described in this paper. The system contains one 128-channel silicon strip detector, four 32-channel Front-End ASICs (FE-ASICs), FPGA-based control circuit, and signal conditioning and power regulation modules, providing energy measurements up to 3.2 MeV per channel. Additionally, a dedicated software tool was developed to control and configure the system, as well as, to automatically characterize and equalize the channels aiming a more uniform response and hence, better energy resolution. It is worth noting that a sigma of 1.6 keV has been achieved for all 128 channels within the lower range of the ASIC (up to 800 keV), while the ASICs were not optimized to work with the specific detector capacitance. This energy resolution is comparable to state of the art Si hybrid-pixel detector Timepix3 [1]. Using a conservative 6-sigma distance to the electronic noise level it was still obtained a system threshold level of 3 keV. This work provides valuable information for particular applications in which a general purpose strip detector-based system could be used efficiently to replace hybrid pixel detectors.