Back-bias impact on variability and BTI for 3D-monolithic 14nm FDSOI SRAMs applications

We fabricated and characterized 14nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078μm ² Static Random Access Memory (SRAM) cells. Temporal and spatial variability as well as sensibility to temperature, supply voltage (VDD) and back bias (Vwell) are extracted. These data evidence that the 14nm SRAM is read-limited, which could be improved by a smart back-bias management [1]. In this work we demonstrate a SOmV Static Noise Margin (SNM) variability improvement (at VDD=0.8V) by back-biasing, without additional Bias Temperature Instability (BTI) stress. Such an assist technique can be eventually leveraged at fine-grain by 3D monolithic integration, owing to local back-planes.