7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions
2020 IEEE International Solid- State Circuits Conference - (ISSCC)(2020)
Abstract
Combinatorial optimization problems ubiquitously appear in AI applications, e.g. machine learning, operational planning, drug discovery, etc. Yet, their NP-hardness makes them notoriously difficult to solve on present computers. To address this problem, new hardware architectures [1, 4], called annealers, have emerged in recent years. Annealers exploit the fact that combinatorial optimization problems can be mapped to the ground state search of an Ising model, where the combination of N spins (σ- ∈ f-1}. x=1, ...,N) with lowest Ising energy represents the optimal solution to the problem (Fig. 7.3.1).
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Key words
hardware architectures,NP-hardness,drug discovery,operational planning,machine learning,complete spin-spin interactions,all-spin-updates-at-once architecture,full-digital annealing processor,512-Spin 0.25M-weight,optimal solution,combinatorial optimization problems
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