7.1 A 3.4-to-13.3tops/w 3.6TOPS Dual-Core Deep-Learning Accelerator for Versatile AI Applications in 7nm 5G Smartphone SoC

Chien-Hung Lin,Chih-Chung Cheng,Yi-Min Tsai,Sheng-Je Hung,Yu-Ting Kuo,Perry H. Wang,Pei-Kuei Tsung,Jeng-Yun Hsu,Wei-Chih Lai,Chia-Hung Liu,Shao-Yu Wang,Chin-Hua Kuo,Chih-Yu Chang,Ming-Hsien Lee,Tsung-Yao Lin,Chih-Cheng Chen

2020 IEEE International Solid- State Circuits Conference - (ISSCC)（2020）

Cited 87|Views51

Key words

5G smartphone SoC,smartphone system-on-a-chip,power budget,required computing efficiency,smartphones,DLA,numerous deep learning accelerators,smartphone applications,satisfactory user experience,versatile AI applications,power 3.0 W,power 1.0 W,size 7.0 nm,byte rate 30.0 GByte/s,byte rate 10.0 GByte/s

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