8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package

2020 IEEE International Solid- State Circuits Conference - (ISSCC)(2020)

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摘要
The Lakefield processor combines heterogeneous 3D die stacking also called Foveros, with hybrid computing to enable a new class of small form factor mobile products. The stacked die and implementation of the 3D package with PoP memory is shown in Fig. 8.1.1. The compute die is on Intel 10nm+ for power-performance and includes the CPU, GPU, IPU, memory and display engine based on IP from the Icelake product family. It includes one Core™ and four Atom™ cores in a hybrid configuration connected using a cache-coherent fabric. Both core types are exposed to the operating system which selects the best core depending on the performance and power characteristics of the workload. The memory subsystem supports LPDDR4X PoP in a 4×16 configuration. The base die is on Intel 22FFL and contains the chipset functionality including PCIe Gen3, USB type-C, storage, audio and a sensor hub. Combining 10nm and 22FFL in 3D enables a large dynamic range of performance and power modes. The 3D dies communicate with a low-power inter-die I/O called the Foveros Die Interface (FDI). The power delivery has been optimized to leverage a PMIC-based power delivery compared to previous to reach the low power and small form factors.
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22FFL hybrid processor system,package-on-package,Lakefield processor,hybrid computing,small form factor mobile products,PoP memory,Intel 10nm,power-performance,display engine,icelake product family,hybrid configuration,cache-coherent fabric,operating system,power characteristics,memory subsystem,LPDDR4X PoP,Intel 22FFL,PCIe Gen3,power modes,low-power inter-die I/O,foveros die interface,PMIC-based power delivery,heterogeneous 3D die stacking
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