Standard-compliant Parallel SystemC Simulation of Loosely-Timed Transaction Level Models
2020 25TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2020（2020）
Key words
standard-compliant parallel SystemC simulation,loosely-timed transaction level models,system-on-chip,time-to-market constraints,virtual prototyping tools,Accellera SystemC reference implementation,standard-compliant SystemC kernel,memory access monitoring,SystemC atomic thread evaluation,Accellera SystemC kernel
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