Data Compression and Re-computation Based Performance Improvement in Multi-Core Architectures

In this paper, we present an approach to improve performance of multi-core embedded architectures utilizing on-chip software-managed memory. The proposed approach targets at data-intensive applications and improves the execution time of such applications by reducing the number of off-chip accesses through data compression and data re-computation. In the proposed approach, after profiling the embedded application, the dataset is divided into blocks and the block access frequencies are calculated. Based on the access frequencies and the size of on-chip memory components, the data is mapped to on-chip SPMs, software-managed on-chip L2 memory and off-chip memory. Then, considering all on-chip data (uncompressed and compressed), the re-computation opportunities that help improving performance are implemented and program code is modified accordingly. The experimental results collected using various benchmark programs show the viability of the proposed approach.