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Evaluations of Electronic Neuron Model for Low Power VLSI Implementation

2019 International SoC Design Conference (ISOCC)(2019)

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Abstract
In this work, the modeling of spiking neurons and their VLSI implement issues are evaluated and discussed in detail in terms of silicon area, power, and stability considering nanometer technologies process, voltage, and temperature variations. Considering low power requirement and stability, Hindmarsh-Rose model turns out to be the best choice for neural network implementation because of its affordable cost and rich neural features. Although other models such as Leaky Integrate-and-Fire model costs less, it is limited by its poor neural plausibility.
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Key words
Neuron Model,Low Power VLSI
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