300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low Power High Performance Logic Applications

W. Rachmady,K. Jun, B. Krist,M. Metz, T. Michaelos,B. Mueller,A. A. Oni,R. Paul,A. Phan, P. Sears, T. Talukdar,A. Agrawal,J. Torres, R. Turkot,L. Wong, H. J. Yoo,J. Kavalieros,S.H. Sung,G. Dewey,S. Chouksey, B. Chu-Kung, G. Elbaz,P. Fischer,C. Y. Huang

international electron devices meeting(2019)

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摘要
We report a short channel high performance Ge PMOS integrated with Si NMOS in sequential monolithic 3D stacking. A layer transfer Ge PMOS with record I ON = 497 μA/μm at I OFF = 8nA/μm and I ON = 630 μA/μm at I OFF = 100nA/μm and V DS = -0.5V is achieved for the first time. Optimized design of metal gate and contact on bottom Si NMOS device layer, along with a low process thermal budget developed for Ge layer transfer and top Ge PMOS device fabrication, allow for sequential stacking with no degradation on each MOS device characteristics. Heterogeneous 3D stacked Ge-Si CMOS inverter is also successfully demonstrated with drive performance maintained on Ge PMOS and Si NMOS.
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关键词
heterogeneous 3D integration,top germanium PMOS device fabrication,metal gate optimized design,short channel high performance germanium PMOS,silicon NMOS device layer,germanium layer transfer,heterogeneous 3D stacked germanium-silicon CMOS inverter,drive performance,MOS device characteristics,low process thermal budget,sequential monolithic 3D stacking,low power high performance logic applications,silicon NMOS,record performance layer transfer germanium PMOS,size 300.0 mm,voltage -0.5 V,Ge-Si
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