Characterization of Threshold Voltage Instability Under Off-State Drain Stress and Its Impact on p-GaN HEMT Performance

The p-GaN gate technology is commonly implemented to achieve normally OFF gallium nitride (GaN) devices. Nonetheless, the threshold voltage instability under OFF-state stress remains a concern. In this article, the characterization technique of threshold voltage shift is proposed and the V _th shift's impact on device performance is investigated. Specifically, a fast V _th the measurement circuit is introduced and validated to successfully characterize both the magnitude and the time-constant of the V _th shift. According to the experimental results, the V _th increases by more than 50% within several μs after the high drain voltage is applied. In contrast, the V _th slowly (tens of seconds) gets back to the static value after the stress is removed. Following the characterization, the threshold voltage instability's impact on the device's static/switching performance is studied experimentally. A knee point shift is observed at low gate voltage, and the static ON-resistance value remains unchanged. Regarding the switching performance, the turn-ON loss increases by >20% after the high drain voltage stress. The change in turn-ON loss can be reduced when the gate resistance is decreased from 20 to 0 Ω. In terms of the turn-OFF loss, the impact of the V _th shift is negligible. It is concluded that time-dependent threshold voltage shift needs to be considered in p-GaN device's modeling, and high gate drive voltage together with low gate resistance is recommended to mitigate the V _th instability's effect on p-GaN high-electron-mobility transistor's performance.