On SFC Low Power Hardware Implementation in FPGAs

The paper presents an idea of automatic synthesis to an FPGA device of a program developed with use of the SFC including actions. The synthesis is oriented to achieve power reduction by creating multiple clock domains and controlling switching activity. A circuit is selectively clocked based on processing activity. Global clock distribution networks are used in order to assure proper operation of a system. Proposed methods automatically split a controller into clock domains and implements all necessary circuitry. The paper is concluded with benchmark experiments that proves energy consumption reduction for proposed methods in reference to standard approach using fully synchronous implementation methodology.