An Internal Schematic View and Simulation of Major Diagonal Mesh Network-on-Chip

NoC is a competent communication for on chip network architectures. It make more efficient the computational and high congestion communication on a single chip. In this paper, we are proposing a NoC topologies, i.e., Major Diagonal Mesh NoC called MD-Mesh NoC. In MD-Mesh NoC the corner of major diagonal linked with each other so that the efficiency of the communication among the corner can be increase. The internal semantic view and register transfer logic (RTL) View has been shown. As number of connections among the nodes increases and number of hopes decreases, performance of packet traversing will get increases. The synthesis and simulation has been done on Vertex 5 FPGA. The hardware parameters like number of slices and memory usage with respect to increase the number of nodes has been calculated on FPGA Vertex 5.