High-Efficiency Stacked Power Amplifier Ic With 23% Fractional Bandwidth For Average Power Tracking Application

This paper presents a two-stage stacked power amplifier integrated circuit (PAIC) for broadband and high efficiency using a 2-mu m InGap/GaAs HBT process with a second-harmonic control circuit and a bias-switching circuit for an average power tracking (APT) application. For APT operation, active bias circuits with a bias switching circuit for the stacked stage were proposed. A simple L-section matching network with a second-harmonic termination circuit was adopted for broad bandwidth and high efficiency. The frequency-independent power and efficiency contours for fundamental and second-harmonic frequency band were extracted at the current-source plane of the transistor. The implemented two-stage PAIC was evaluated using a long-term evolution signal with a peak-to-average power ratio (PAPR) of 7.5 dB and a signal bandwidth of 10 MHz. From 1.55 to 1.95 GHz, the power amplifier exhibited average output power ranging from 27.4 to 28.5 dBm, a power gain of more than 28.6 dB, and a power-added efficiency (PAE) of 36.5 to 41.2% at an ACLR of -30 dBc. At an average output power back-off of 5 dB, the PAE improved to 29.5% with APT using an external buck-boost dc-dc converter, while it was 18.7% without APT.