Design of Metal-Oxide-Metal Capacitors in a 65-nm CMOS Process

Three types of metal–oxide–metal capacitors fabricated in a 65-nm CMOS process are compared. The HPP structure utilizing only the vertical electric field exhibits a higher capacitance density of 0.2, 0.64, and 0.76 fF/μm2 as the number of stacked metal layers increase to four, six, and eight, respectively. The VPP structure, which utilizes only the horizontal electric field, exhibits a relatively small capacitance density of 0.27 fF/μm2. In contrast, the PW structure using the vertical and horizontal electric fields exhibits the highest capacitance density of 0.88 fF/μm2. In the given CMOS process, it is observed that the HPP structure with many metal layers and the PW structure are advantageous at millimeter-wave frequencies, offering a suitable replacement for metal–insulator–metal capacitors.