Effects of the physical parameter on gate all around FET

As the devices are getting compact, the size of transistors reduces day by day; however, with certain limitations. Due to miniaturization, the characteristics of the transistor change due to quantum mechanical effects and the present scenario, analytically modeled surface potential-based gate all around (GAA) FET model by solving 1-D Poisson’s equation, approximation method and using necessary boundary condition. Here, the change in channel material (Si, InP, GaAs, InAs and Ge), channel radius (varied from 6 nm to 10 nm), oxide thickness (changed from 2 nm to 5 nm), drain to source voltage (varied from −0.5 V to 0.5 V), Source/Drain doping (varied from 10 17 to 10 22 /cm 3 ) and temperature (from 0 to 300 K) of the transistor, surface potential changes from −1.6 V to 1.3 V approx. respectively, considered as the GAA FET parameters. The proposed novel model exhibits better control over hot carrier effect, Drain Induced Barrier Lowering (DIBL), reduced threshold voltage and other such short channel effects in the GAA FET. Moreover, the I–V characteristics of the GAA FET were analyzed. The MATLAB code is used for modeling of the GAA FET nanowire transistor.